/* * interrupt and exception entry stubs. * * the CPU pushes, in order: [error code,] RIP, CS, RFLAGS, RSP [, SS]. vectors * that have no error code do not push one, so each stub first normalises the * frame to a single shape by supplying a zero, and pushes the vector number. * the common path therefore always sees: * * [rsp+0] vector * [rsp+8] error code (0 for vectors that do not push one) * [rsp+16] RIP * [rsp+24] CS * [rsp+32] RFLAGS * [rsp+40] RSP * * the common path then pushes the fifteen general-purpose registers, so the * frame handed to C (struct interrupt_frame in idt.h) is: * * rax rbx rcx rdx rbp rsi rdi r8 r9 r10 r11 r12 r13 r14 r15 * vector error_code rip cs rflags * * everything runs on the interrupted stack: our GDT has ring-0 code and data * only, so there is no privilege change and therefore no stack switch. * * not yet done: the FPU/SSE/AVX state is not saved or restored. that is safe * today because nothing touches the FPU from interrupt context, but it must be * fixed before user-space transitions or any FPU use. * * the 256 stub bodies below are a mechanical expansion ; there is one per vector * because only a stub that knows its own number can supply it. */ .text .macro ISR_NOERR num isr_stub_\num: pushq $0 /* no CPU-pushed error code */ pushq $\num jmp isr_common .endm .macro ISR_ERR num isr_stub_\num: pushq $\num /* error code is already on the stack */ jmp isr_common .endm /* vectors that push an error code: #DF 8, #TS 10, #NP 11, #SS 12, #GP 13, #PF 14, #AC 17, #CP 21, #VC 29, #SX 30. */ ISR_NOERR 0 ISR_NOERR 1 ISR_NOERR 2 ISR_NOERR 3 ISR_NOERR 4 ISR_NOERR 5 ISR_NOERR 6 ISR_NOERR 7 ISR_ERR 8 ISR_NOERR 9 ISR_ERR 10 ISR_ERR 11 ISR_ERR 12 ISR_ERR 13 ISR_ERR 14 ISR_NOERR 15 ISR_NOERR 16 ISR_ERR 17 ISR_NOERR 18 ISR_NOERR 19 ISR_NOERR 20 ISR_ERR 21 ISR_NOERR 22 ISR_NOERR 23 ISR_NOERR 24 ISR_NOERR 25 ISR_NOERR 26 ISR_NOERR 27 ISR_NOERR 28 ISR_ERR 29 ISR_ERR 30 ISR_NOERR 31 ISR_NOERR 32 ISR_NOERR 33 ISR_NOERR 34 ISR_NOERR 35 ISR_NOERR 36 ISR_NOERR 37 ISR_NOERR 38 ISR_NOERR 39 ISR_NOERR 40 ISR_NOERR 41 ISR_NOERR 42 ISR_NOERR 43 ISR_NOERR 44 ISR_NOERR 45 ISR_NOERR 46 ISR_NOERR 47 ISR_NOERR 48 ISR_NOERR 49 ISR_NOERR 50 ISR_NOERR 51 ISR_NOERR 52 ISR_NOERR 53 ISR_NOERR 54 ISR_NOERR 55 ISR_NOERR 56 ISR_NOERR 57 ISR_NOERR 58 ISR_NOERR 59 ISR_NOERR 60 ISR_NOERR 61 ISR_NOERR 62 ISR_NOERR 63 ISR_NOERR 64 ISR_NOERR 65 ISR_NOERR 66 ISR_NOERR 67 ISR_NOERR 68 ISR_NOERR 69 ISR_NOERR 70 ISR_NOERR 71 ISR_NOERR 72 ISR_NOERR 73 ISR_NOERR 74 ISR_NOERR 75 ISR_NOERR 76 ISR_NOERR 77 ISR_NOERR 78 ISR_NOERR 79 ISR_NOERR 80 ISR_NOERR 81 ISR_NOERR 82 ISR_NOERR 83 ISR_NOERR 84 ISR_NOERR 85 ISR_NOERR 86 ISR_NOERR 87 ISR_NOERR 88 ISR_NOERR 89 ISR_NOERR 90 ISR_NOERR 91 ISR_NOERR 92 ISR_NOERR 93 ISR_NOERR 94 ISR_NOERR 95 ISR_NOERR 96 ISR_NOERR 97 ISR_NOERR 98 ISR_NOERR 99 ISR_NOERR 100 ISR_NOERR 101 ISR_NOERR 102 ISR_NOERR 103 ISR_NOERR 104 ISR_NOERR 105 ISR_NOERR 106 ISR_NOERR 107 ISR_NOERR 108 ISR_NOERR 109 ISR_NOERR 110 ISR_NOERR 111 ISR_NOERR 112 ISR_NOERR 113 ISR_NOERR 114 ISR_NOERR 115 ISR_NOERR 116 ISR_NOERR 117 ISR_NOERR 118 ISR_NOERR 119 ISR_NOERR 120 ISR_NOERR 121 ISR_NOERR 122 ISR_NOERR 123 ISR_NOERR 124 ISR_NOERR 125 ISR_NOERR 126 ISR_NOERR 127 ISR_NOERR 128 ISR_NOERR 129 ISR_NOERR 130 ISR_NOERR 131 ISR_NOERR 132 ISR_NOERR 133 ISR_NOERR 134 ISR_NOERR 135 ISR_NOERR 136 ISR_NOERR 137 ISR_NOERR 138 ISR_NOERR 139 ISR_NOERR 140 ISR_NOERR 141 ISR_NOERR 142 ISR_NOERR 143 ISR_NOERR 144 ISR_NOERR 145 ISR_NOERR 146 ISR_NOERR 147 ISR_NOERR 148 ISR_NOERR 149 ISR_NOERR 150 ISR_NOERR 151 ISR_NOERR 152 ISR_NOERR 153 ISR_NOERR 154 ISR_NOERR 155 ISR_NOERR 156 ISR_NOERR 157 ISR_NOERR 158 ISR_NOERR 159 ISR_NOERR 160 ISR_NOERR 161 ISR_NOERR 162 ISR_NOERR 163 ISR_NOERR 164 ISR_NOERR 165 ISR_NOERR 166 ISR_NOERR 167 ISR_NOERR 168 ISR_NOERR 169 ISR_NOERR 170 ISR_NOERR 171 ISR_NOERR 172 ISR_NOERR 173 ISR_NOERR 174 ISR_NOERR 175 ISR_NOERR 176 ISR_NOERR 177 ISR_NOERR 178 ISR_NOERR 179 ISR_NOERR 180 ISR_NOERR 181 ISR_NOERR 182 ISR_NOERR 183 ISR_NOERR 184 ISR_NOERR 185 ISR_NOERR 186 ISR_NOERR 187 ISR_NOERR 188 ISR_NOERR 189 ISR_NOERR 190 ISR_NOERR 191 ISR_NOERR 192 ISR_NOERR 193 ISR_NOERR 194 ISR_NOERR 195 ISR_NOERR 196 ISR_NOERR 197 ISR_NOERR 198 ISR_NOERR 199 ISR_NOERR 200 ISR_NOERR 201 ISR_NOERR 202 ISR_NOERR 203 ISR_NOERR 204 ISR_NOERR 205 ISR_NOERR 206 ISR_NOERR 207 ISR_NOERR 208 ISR_NOERR 209 ISR_NOERR 210 ISR_NOERR 211 ISR_NOERR 212 ISR_NOERR 213 ISR_NOERR 214 ISR_NOERR 215 ISR_NOERR 216 ISR_NOERR 217 ISR_NOERR 218 ISR_NOERR 219 ISR_NOERR 220 ISR_NOERR 221 ISR_NOERR 222 ISR_NOERR 223 ISR_NOERR 224 ISR_NOERR 225 ISR_NOERR 226 ISR_NOERR 227 ISR_NOERR 228 ISR_NOERR 229 ISR_NOERR 230 ISR_NOERR 231 ISR_NOERR 232 ISR_NOERR 233 ISR_NOERR 234 ISR_NOERR 235 ISR_NOERR 236 ISR_NOERR 237 ISR_NOERR 238 ISR_NOERR 239 ISR_NOERR 240 ISR_NOERR 241 ISR_NOERR 242 ISR_NOERR 243 ISR_NOERR 244 ISR_NOERR 245 ISR_NOERR 246 ISR_NOERR 247 ISR_NOERR 248 ISR_NOERR 249 ISR_NOERR 250 ISR_NOERR 251 ISR_NOERR 252 ISR_NOERR 253 ISR_NOERR 254 ISR_NOERR 255 isr_common: cld /* the ABI requires DF = 0 on entry */ pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %r11 pushq %r10 pushq %r9 pushq %r8 pushq %rdi pushq %rsi pushq %rbp pushq %rbx pushq %rdx pushq %rcx pushq %rax /* * RBX was pushed above, so the live register is free scratch. RSP may no * longer be 16-byte aligned after an odd number of pushes, so align it * and keep the original in RBX for the restore. * * NB: the frame pointer goes in RCX, not RDI. the kernel targets * x86_64-unknown-windows, so the Microsoft x64 ABI applies and arg0 is * RCX. the System V convention would silently corrupt the dispatch. */ movq %rsp, %rbx movq %rbx, %rcx /* arg0: const struct interrupt_frame * */ andq $-16, %rsp subq $0x20, %rsp /* 32 bytes of shadow space for the callee */ call interrupt_dispatch movq %rbx, %rsp popq %rax popq %rcx popq %rdx popq %rbx popq %rbp popq %rsi popq %rdi popq %r8 popq %r9 popq %r10 popq %r11 popq %r12 popq %r13 popq %r14 popq %r15 addq $0x10, %rsp /* drop the vector and the error code */ iretq /* restores RIP, CS, RFLAGS (including IF) */ /* one 64-bit pointer per vector, consumed by idt_init() to fill the IDT. */ .data .balign 8 .globl isr_stub_table isr_stub_table: .quad isr_stub_0 .quad isr_stub_1 .quad isr_stub_2 .quad isr_stub_3 .quad isr_stub_4 .quad isr_stub_5 .quad isr_stub_6 .quad isr_stub_7 .quad isr_stub_8 .quad isr_stub_9 .quad isr_stub_10 .quad isr_stub_11 .quad isr_stub_12 .quad isr_stub_13 .quad isr_stub_14 .quad isr_stub_15 .quad isr_stub_16 .quad isr_stub_17 .quad isr_stub_18 .quad isr_stub_19 .quad isr_stub_20 .quad isr_stub_21 .quad isr_stub_22 .quad isr_stub_23 .quad isr_stub_24 .quad isr_stub_25 .quad isr_stub_26 .quad isr_stub_27 .quad isr_stub_28 .quad isr_stub_29 .quad isr_stub_30 .quad isr_stub_31 .quad isr_stub_32 .quad isr_stub_33 .quad isr_stub_34 .quad isr_stub_35 .quad isr_stub_36 .quad isr_stub_37 .quad isr_stub_38 .quad isr_stub_39 .quad isr_stub_40 .quad isr_stub_41 .quad isr_stub_42 .quad isr_stub_43 .quad isr_stub_44 .quad isr_stub_45 .quad isr_stub_46 .quad isr_stub_47 .quad isr_stub_48 .quad isr_stub_49 .quad isr_stub_50 .quad isr_stub_51 .quad isr_stub_52 .quad isr_stub_53 .quad isr_stub_54 .quad isr_stub_55 .quad isr_stub_56 .quad isr_stub_57 .quad isr_stub_58 .quad isr_stub_59 .quad isr_stub_60 .quad isr_stub_61 .quad isr_stub_62 .quad isr_stub_63 .quad isr_stub_64 .quad isr_stub_65 .quad isr_stub_66 .quad isr_stub_67 .quad isr_stub_68 .quad isr_stub_69 .quad isr_stub_70 .quad isr_stub_71 .quad isr_stub_72 .quad isr_stub_73 .quad isr_stub_74 .quad isr_stub_75 .quad isr_stub_76 .quad isr_stub_77 .quad isr_stub_78 .quad isr_stub_79 .quad isr_stub_80 .quad isr_stub_81 .quad isr_stub_82 .quad isr_stub_83 .quad isr_stub_84 .quad isr_stub_85 .quad isr_stub_86 .quad isr_stub_87 .quad isr_stub_88 .quad isr_stub_89 .quad isr_stub_90 .quad isr_stub_91 .quad isr_stub_92 .quad isr_stub_93 .quad isr_stub_94 .quad isr_stub_95 .quad isr_stub_96 .quad isr_stub_97 .quad isr_stub_98 .quad isr_stub_99 .quad isr_stub_100 .quad isr_stub_101 .quad isr_stub_102 .quad isr_stub_103 .quad isr_stub_104 .quad isr_stub_105 .quad isr_stub_106 .quad isr_stub_107 .quad isr_stub_108 .quad isr_stub_109 .quad isr_stub_110 .quad isr_stub_111 .quad isr_stub_112 .quad isr_stub_113 .quad isr_stub_114 .quad isr_stub_115 .quad isr_stub_116 .quad isr_stub_117 .quad isr_stub_118 .quad isr_stub_119 .quad isr_stub_120 .quad isr_stub_121 .quad isr_stub_122 .quad isr_stub_123 .quad isr_stub_124 .quad isr_stub_125 .quad isr_stub_126 .quad isr_stub_127 .quad isr_stub_128 .quad isr_stub_129 .quad isr_stub_130 .quad isr_stub_131 .quad isr_stub_132 .quad isr_stub_133 .quad isr_stub_134 .quad isr_stub_135 .quad isr_stub_136 .quad isr_stub_137 .quad isr_stub_138 .quad isr_stub_139 .quad isr_stub_140 .quad isr_stub_141 .quad isr_stub_142 .quad isr_stub_143 .quad isr_stub_144 .quad isr_stub_145 .quad isr_stub_146 .quad isr_stub_147 .quad isr_stub_148 .quad isr_stub_149 .quad isr_stub_150 .quad isr_stub_151 .quad isr_stub_152 .quad isr_stub_153 .quad isr_stub_154 .quad isr_stub_155 .quad isr_stub_156 .quad isr_stub_157 .quad isr_stub_158 .quad isr_stub_159 .quad isr_stub_160 .quad isr_stub_161 .quad isr_stub_162 .quad isr_stub_163 .quad isr_stub_164 .quad isr_stub_165 .quad isr_stub_166 .quad isr_stub_167 .quad isr_stub_168 .quad isr_stub_169 .quad isr_stub_170 .quad isr_stub_171 .quad isr_stub_172 .quad isr_stub_173 .quad isr_stub_174 .quad isr_stub_175 .quad isr_stub_176 .quad isr_stub_177 .quad isr_stub_178 .quad isr_stub_179 .quad isr_stub_180 .quad isr_stub_181 .quad isr_stub_182 .quad isr_stub_183 .quad isr_stub_184 .quad isr_stub_185 .quad isr_stub_186 .quad isr_stub_187 .quad isr_stub_188 .quad isr_stub_189 .quad isr_stub_190 .quad isr_stub_191 .quad isr_stub_192 .quad isr_stub_193 .quad isr_stub_194 .quad isr_stub_195 .quad isr_stub_196 .quad isr_stub_197 .quad isr_stub_198 .quad isr_stub_199 .quad isr_stub_200 .quad isr_stub_201 .quad isr_stub_202 .quad isr_stub_203 .quad isr_stub_204 .quad isr_stub_205 .quad isr_stub_206 .quad isr_stub_207 .quad isr_stub_208 .quad isr_stub_209 .quad isr_stub_210 .quad isr_stub_211 .quad isr_stub_212 .quad isr_stub_213 .quad isr_stub_214 .quad isr_stub_215 .quad isr_stub_216 .quad isr_stub_217 .quad isr_stub_218 .quad isr_stub_219 .quad isr_stub_220 .quad isr_stub_221 .quad isr_stub_222 .quad isr_stub_223 .quad isr_stub_224 .quad isr_stub_225 .quad isr_stub_226 .quad isr_stub_227 .quad isr_stub_228 .quad isr_stub_229 .quad isr_stub_230 .quad isr_stub_231 .quad isr_stub_232 .quad isr_stub_233 .quad isr_stub_234 .quad isr_stub_235 .quad isr_stub_236 .quad isr_stub_237 .quad isr_stub_238 .quad isr_stub_239 .quad isr_stub_240 .quad isr_stub_241 .quad isr_stub_242 .quad isr_stub_243 .quad isr_stub_244 .quad isr_stub_245 .quad isr_stub_246 .quad isr_stub_247 .quad isr_stub_248 .quad isr_stub_249 .quad isr_stub_250 .quad isr_stub_251 .quad isr_stub_252 .quad isr_stub_253 .quad isr_stub_254 .quad isr_stub_255