furix
cute os
arch/x86_64/isr.S
13610 bytes raw
1/*
2 * interrupt and exception entry stubs.
3 *
4 * the CPU pushes, in order: [error code,] RIP, CS, RFLAGS, RSP [, SS]. vectors
5 * that have no error code do not push one, so each stub first normalises the
6 * frame to a single shape by supplying a zero, and pushes the vector number.
7 * the common path therefore always sees:
8 *
9 * [rsp+0] vector
10 * [rsp+8] error code (0 for vectors that do not push one)
11 * [rsp+16] RIP
12 * [rsp+24] CS
13 * [rsp+32] RFLAGS
14 * [rsp+40] RSP
15 *
16 * the common path then pushes the fifteen general-purpose registers, so the
17 * frame handed to C (struct interrupt_frame in idt.h) is:
18 *
19 * rax rbx rcx rdx rbp rsi rdi r8 r9 r10 r11 r12 r13 r14 r15
20 * vector error_code rip cs rflags
21 *
22 * everything runs on the interrupted stack: our GDT has ring-0 code and data
23 * only, so there is no privilege change and therefore no stack switch.
24 *
25 * not yet done: the FPU/SSE/AVX state is not saved or restored. that is safe
26 * today because nothing touches the FPU from interrupt context, but it must be
27 * fixed before user-space transitions or any FPU use.
28 *
29 * the 256 stub bodies below are a mechanical expansion ; there is one per vector
30 * because only a stub that knows its own number can supply it.
31 */
32
33.text
34
35.macro ISR_NOERR num
36
37
38isr_stub_\num:
39
40 pushq $0 /* no CPU-pushed error code */
41 pushq $\num
42 jmp isr_common
43.endm
44
45.macro ISR_ERR num
46
47
48isr_stub_\num:
49
50 pushq $\num /* error code is already on the stack */
51 jmp isr_common
52.endm
53
54/* vectors that push an error code: #DF 8, #TS 10, #NP 11, #SS 12, #GP 13,
55
56 #PF 14, #AC 17, #CP 21, #VC 29, #SX 30. */
57 ISR_NOERR 0
58 ISR_NOERR 1
59 ISR_NOERR 2
60 ISR_NOERR 3
61 ISR_NOERR 4
62 ISR_NOERR 5
63 ISR_NOERR 6
64 ISR_NOERR 7
65 ISR_ERR 8
66 ISR_NOERR 9
67 ISR_ERR 10
68 ISR_ERR 11
69 ISR_ERR 12
70 ISR_ERR 13
71 ISR_ERR 14
72 ISR_NOERR 15
73 ISR_NOERR 16
74 ISR_ERR 17
75 ISR_NOERR 18
76 ISR_NOERR 19
77 ISR_NOERR 20
78 ISR_ERR 21
79 ISR_NOERR 22
80 ISR_NOERR 23
81 ISR_NOERR 24
82 ISR_NOERR 25
83 ISR_NOERR 26
84 ISR_NOERR 27
85 ISR_NOERR 28
86 ISR_ERR 29
87 ISR_ERR 30
88 ISR_NOERR 31
89 ISR_NOERR 32
90 ISR_NOERR 33
91 ISR_NOERR 34
92 ISR_NOERR 35
93 ISR_NOERR 36
94 ISR_NOERR 37
95 ISR_NOERR 38
96 ISR_NOERR 39
97 ISR_NOERR 40
98 ISR_NOERR 41
99 ISR_NOERR 42
100 ISR_NOERR 43
101 ISR_NOERR 44
102 ISR_NOERR 45
103 ISR_NOERR 46
104 ISR_NOERR 47
105 ISR_NOERR 48
106 ISR_NOERR 49
107 ISR_NOERR 50
108 ISR_NOERR 51
109 ISR_NOERR 52
110 ISR_NOERR 53
111 ISR_NOERR 54
112 ISR_NOERR 55
113 ISR_NOERR 56
114 ISR_NOERR 57
115 ISR_NOERR 58
116 ISR_NOERR 59
117 ISR_NOERR 60
118 ISR_NOERR 61
119 ISR_NOERR 62
120 ISR_NOERR 63
121 ISR_NOERR 64
122 ISR_NOERR 65
123 ISR_NOERR 66
124 ISR_NOERR 67
125 ISR_NOERR 68
126 ISR_NOERR 69
127 ISR_NOERR 70
128 ISR_NOERR 71
129 ISR_NOERR 72
130 ISR_NOERR 73
131 ISR_NOERR 74
132 ISR_NOERR 75
133 ISR_NOERR 76
134 ISR_NOERR 77
135 ISR_NOERR 78
136 ISR_NOERR 79
137 ISR_NOERR 80
138 ISR_NOERR 81
139 ISR_NOERR 82
140 ISR_NOERR 83
141 ISR_NOERR 84
142 ISR_NOERR 85
143 ISR_NOERR 86
144 ISR_NOERR 87
145 ISR_NOERR 88
146 ISR_NOERR 89
147 ISR_NOERR 90
148 ISR_NOERR 91
149 ISR_NOERR 92
150 ISR_NOERR 93
151 ISR_NOERR 94
152 ISR_NOERR 95
153 ISR_NOERR 96
154 ISR_NOERR 97
155 ISR_NOERR 98
156 ISR_NOERR 99
157 ISR_NOERR 100
158 ISR_NOERR 101
159 ISR_NOERR 102
160 ISR_NOERR 103
161 ISR_NOERR 104
162 ISR_NOERR 105
163 ISR_NOERR 106
164 ISR_NOERR 107
165 ISR_NOERR 108
166 ISR_NOERR 109
167 ISR_NOERR 110
168 ISR_NOERR 111
169 ISR_NOERR 112
170 ISR_NOERR 113
171 ISR_NOERR 114
172 ISR_NOERR 115
173 ISR_NOERR 116
174 ISR_NOERR 117
175 ISR_NOERR 118
176 ISR_NOERR 119
177 ISR_NOERR 120
178 ISR_NOERR 121
179 ISR_NOERR 122
180 ISR_NOERR 123
181 ISR_NOERR 124
182 ISR_NOERR 125
183 ISR_NOERR 126
184 ISR_NOERR 127
185 ISR_NOERR 128
186 ISR_NOERR 129
187 ISR_NOERR 130
188 ISR_NOERR 131
189 ISR_NOERR 132
190 ISR_NOERR 133
191 ISR_NOERR 134
192 ISR_NOERR 135
193 ISR_NOERR 136
194 ISR_NOERR 137
195 ISR_NOERR 138
196 ISR_NOERR 139
197 ISR_NOERR 140
198 ISR_NOERR 141
199 ISR_NOERR 142
200 ISR_NOERR 143
201 ISR_NOERR 144
202 ISR_NOERR 145
203 ISR_NOERR 146
204 ISR_NOERR 147
205 ISR_NOERR 148
206 ISR_NOERR 149
207 ISR_NOERR 150
208 ISR_NOERR 151
209 ISR_NOERR 152
210 ISR_NOERR 153
211 ISR_NOERR 154
212 ISR_NOERR 155
213 ISR_NOERR 156
214 ISR_NOERR 157
215 ISR_NOERR 158
216 ISR_NOERR 159
217 ISR_NOERR 160
218 ISR_NOERR 161
219 ISR_NOERR 162
220 ISR_NOERR 163
221 ISR_NOERR 164
222 ISR_NOERR 165
223 ISR_NOERR 166
224 ISR_NOERR 167
225 ISR_NOERR 168
226 ISR_NOERR 169
227 ISR_NOERR 170
228 ISR_NOERR 171
229 ISR_NOERR 172
230 ISR_NOERR 173
231 ISR_NOERR 174
232 ISR_NOERR 175
233 ISR_NOERR 176
234 ISR_NOERR 177
235 ISR_NOERR 178
236 ISR_NOERR 179
237 ISR_NOERR 180
238 ISR_NOERR 181
239 ISR_NOERR 182
240 ISR_NOERR 183
241 ISR_NOERR 184
242 ISR_NOERR 185
243 ISR_NOERR 186
244 ISR_NOERR 187
245 ISR_NOERR 188
246 ISR_NOERR 189
247 ISR_NOERR 190
248 ISR_NOERR 191
249 ISR_NOERR 192
250 ISR_NOERR 193
251 ISR_NOERR 194
252 ISR_NOERR 195
253 ISR_NOERR 196
254 ISR_NOERR 197
255 ISR_NOERR 198
256 ISR_NOERR 199
257 ISR_NOERR 200
258 ISR_NOERR 201
259 ISR_NOERR 202
260 ISR_NOERR 203
261 ISR_NOERR 204
262 ISR_NOERR 205
263 ISR_NOERR 206
264 ISR_NOERR 207
265 ISR_NOERR 208
266 ISR_NOERR 209
267 ISR_NOERR 210
268 ISR_NOERR 211
269 ISR_NOERR 212
270 ISR_NOERR 213
271 ISR_NOERR 214
272 ISR_NOERR 215
273 ISR_NOERR 216
274 ISR_NOERR 217
275 ISR_NOERR 218
276 ISR_NOERR 219
277 ISR_NOERR 220
278 ISR_NOERR 221
279 ISR_NOERR 222
280 ISR_NOERR 223
281 ISR_NOERR 224
282 ISR_NOERR 225
283 ISR_NOERR 226
284 ISR_NOERR 227
285 ISR_NOERR 228
286 ISR_NOERR 229
287 ISR_NOERR 230
288 ISR_NOERR 231
289 ISR_NOERR 232
290 ISR_NOERR 233
291 ISR_NOERR 234
292 ISR_NOERR 235
293 ISR_NOERR 236
294 ISR_NOERR 237
295 ISR_NOERR 238
296 ISR_NOERR 239
297 ISR_NOERR 240
298 ISR_NOERR 241
299 ISR_NOERR 242
300 ISR_NOERR 243
301 ISR_NOERR 244
302 ISR_NOERR 245
303 ISR_NOERR 246
304 ISR_NOERR 247
305 ISR_NOERR 248
306 ISR_NOERR 249
307 ISR_NOERR 250
308 ISR_NOERR 251
309 ISR_NOERR 252
310 ISR_NOERR 253
311 ISR_NOERR 254
312 ISR_NOERR 255
313
314isr_common:
315
316 cld /* the ABI requires DF = 0 on entry */
317
318 pushq %r15
319 pushq %r14
320 pushq %r13
321 pushq %r12
322 pushq %r11
323 pushq %r10
324 pushq %r9
325 pushq %r8
326 pushq %rdi
327 pushq %rsi
328 pushq %rbp
329 pushq %rbx
330 pushq %rdx
331 pushq %rcx
332 pushq %rax
333
334 /*
335 * RBX was pushed above, so the live register is free scratch. RSP may no
336 * longer be 16-byte aligned after an odd number of pushes, so align it
337 * and keep the original in RBX for the restore.
338 *
339 * NB: the frame pointer goes in RCX, not RDI. the kernel targets
340 * x86_64-unknown-windows, so the Microsoft x64 ABI applies and arg0 is
341 * RCX. the System V convention would silently corrupt the dispatch.
342 */
343 movq %rsp, %rbx
344 movq %rbx, %rcx /* arg0: const struct interrupt_frame * */
345 andq $-16, %rsp
346 subq $0x20, %rsp /* 32 bytes of shadow space for the callee */
347 call interrupt_dispatch
348 movq %rbx, %rsp
349
350 popq %rax
351 popq %rcx
352 popq %rdx
353 popq %rbx
354 popq %rbp
355 popq %rsi
356 popq %rdi
357 popq %r8
358 popq %r9
359 popq %r10
360 popq %r11
361 popq %r12
362 popq %r13
363 popq %r14
364 popq %r15
365
366 addq $0x10, %rsp /* drop the vector and the error code */
367 iretq /* restores RIP, CS, RFLAGS (including IF) */
368
369/* one 64-bit pointer per vector, consumed by idt_init() to fill the IDT. */
370.data
371.balign 8
372.globl isr_stub_table
373
374
375isr_stub_table:
376
377 .quad isr_stub_0
378 .quad isr_stub_1
379 .quad isr_stub_2
380 .quad isr_stub_3
381 .quad isr_stub_4
382 .quad isr_stub_5
383 .quad isr_stub_6
384 .quad isr_stub_7
385 .quad isr_stub_8
386 .quad isr_stub_9
387 .quad isr_stub_10
388 .quad isr_stub_11
389 .quad isr_stub_12
390 .quad isr_stub_13
391 .quad isr_stub_14
392 .quad isr_stub_15
393 .quad isr_stub_16
394 .quad isr_stub_17
395 .quad isr_stub_18
396 .quad isr_stub_19
397 .quad isr_stub_20
398 .quad isr_stub_21
399 .quad isr_stub_22
400 .quad isr_stub_23
401 .quad isr_stub_24
402 .quad isr_stub_25
403 .quad isr_stub_26
404 .quad isr_stub_27
405 .quad isr_stub_28
406 .quad isr_stub_29
407 .quad isr_stub_30
408 .quad isr_stub_31
409 .quad isr_stub_32
410 .quad isr_stub_33
411 .quad isr_stub_34
412 .quad isr_stub_35
413 .quad isr_stub_36
414 .quad isr_stub_37
415 .quad isr_stub_38
416 .quad isr_stub_39
417 .quad isr_stub_40
418 .quad isr_stub_41
419 .quad isr_stub_42
420 .quad isr_stub_43
421 .quad isr_stub_44
422 .quad isr_stub_45
423 .quad isr_stub_46
424 .quad isr_stub_47
425 .quad isr_stub_48
426 .quad isr_stub_49
427 .quad isr_stub_50
428 .quad isr_stub_51
429 .quad isr_stub_52
430 .quad isr_stub_53
431 .quad isr_stub_54
432 .quad isr_stub_55
433 .quad isr_stub_56
434 .quad isr_stub_57
435 .quad isr_stub_58
436 .quad isr_stub_59
437 .quad isr_stub_60
438 .quad isr_stub_61
439 .quad isr_stub_62
440 .quad isr_stub_63
441 .quad isr_stub_64
442 .quad isr_stub_65
443 .quad isr_stub_66
444 .quad isr_stub_67
445 .quad isr_stub_68
446 .quad isr_stub_69
447 .quad isr_stub_70
448 .quad isr_stub_71
449 .quad isr_stub_72
450 .quad isr_stub_73
451 .quad isr_stub_74
452 .quad isr_stub_75
453 .quad isr_stub_76
454 .quad isr_stub_77
455 .quad isr_stub_78
456 .quad isr_stub_79
457 .quad isr_stub_80
458 .quad isr_stub_81
459 .quad isr_stub_82
460 .quad isr_stub_83
461 .quad isr_stub_84
462 .quad isr_stub_85
463 .quad isr_stub_86
464 .quad isr_stub_87
465 .quad isr_stub_88
466 .quad isr_stub_89
467 .quad isr_stub_90
468 .quad isr_stub_91
469 .quad isr_stub_92
470 .quad isr_stub_93
471 .quad isr_stub_94
472 .quad isr_stub_95
473 .quad isr_stub_96
474 .quad isr_stub_97
475 .quad isr_stub_98
476 .quad isr_stub_99
477 .quad isr_stub_100
478 .quad isr_stub_101
479 .quad isr_stub_102
480 .quad isr_stub_103
481 .quad isr_stub_104
482 .quad isr_stub_105
483 .quad isr_stub_106
484 .quad isr_stub_107
485 .quad isr_stub_108
486 .quad isr_stub_109
487 .quad isr_stub_110
488 .quad isr_stub_111
489 .quad isr_stub_112
490 .quad isr_stub_113
491 .quad isr_stub_114
492 .quad isr_stub_115
493 .quad isr_stub_116
494 .quad isr_stub_117
495 .quad isr_stub_118
496 .quad isr_stub_119
497 .quad isr_stub_120
498 .quad isr_stub_121
499 .quad isr_stub_122
500 .quad isr_stub_123
501 .quad isr_stub_124
502 .quad isr_stub_125
503 .quad isr_stub_126
504 .quad isr_stub_127
505 .quad isr_stub_128
506 .quad isr_stub_129
507 .quad isr_stub_130
508 .quad isr_stub_131
509 .quad isr_stub_132
510 .quad isr_stub_133
511 .quad isr_stub_134
512 .quad isr_stub_135
513 .quad isr_stub_136
514 .quad isr_stub_137
515 .quad isr_stub_138
516 .quad isr_stub_139
517 .quad isr_stub_140
518 .quad isr_stub_141
519 .quad isr_stub_142
520 .quad isr_stub_143
521 .quad isr_stub_144
522 .quad isr_stub_145
523 .quad isr_stub_146
524 .quad isr_stub_147
525 .quad isr_stub_148
526 .quad isr_stub_149
527 .quad isr_stub_150
528 .quad isr_stub_151
529 .quad isr_stub_152
530 .quad isr_stub_153
531 .quad isr_stub_154
532 .quad isr_stub_155
533 .quad isr_stub_156
534 .quad isr_stub_157
535 .quad isr_stub_158
536 .quad isr_stub_159
537 .quad isr_stub_160
538 .quad isr_stub_161
539 .quad isr_stub_162
540 .quad isr_stub_163
541 .quad isr_stub_164
542 .quad isr_stub_165
543 .quad isr_stub_166
544 .quad isr_stub_167
545 .quad isr_stub_168
546 .quad isr_stub_169
547 .quad isr_stub_170
548 .quad isr_stub_171
549 .quad isr_stub_172
550 .quad isr_stub_173
551 .quad isr_stub_174
552 .quad isr_stub_175
553 .quad isr_stub_176
554 .quad isr_stub_177
555 .quad isr_stub_178
556 .quad isr_stub_179
557 .quad isr_stub_180
558 .quad isr_stub_181
559 .quad isr_stub_182
560 .quad isr_stub_183
561 .quad isr_stub_184
562 .quad isr_stub_185
563 .quad isr_stub_186
564 .quad isr_stub_187
565 .quad isr_stub_188
566 .quad isr_stub_189
567 .quad isr_stub_190
568 .quad isr_stub_191
569 .quad isr_stub_192
570 .quad isr_stub_193
571 .quad isr_stub_194
572 .quad isr_stub_195
573 .quad isr_stub_196
574 .quad isr_stub_197
575 .quad isr_stub_198
576 .quad isr_stub_199
577 .quad isr_stub_200
578 .quad isr_stub_201
579 .quad isr_stub_202
580 .quad isr_stub_203
581 .quad isr_stub_204
582 .quad isr_stub_205
583 .quad isr_stub_206
584 .quad isr_stub_207
585 .quad isr_stub_208
586 .quad isr_stub_209
587 .quad isr_stub_210
588 .quad isr_stub_211
589 .quad isr_stub_212
590 .quad isr_stub_213
591 .quad isr_stub_214
592 .quad isr_stub_215
593 .quad isr_stub_216
594 .quad isr_stub_217
595 .quad isr_stub_218
596 .quad isr_stub_219
597 .quad isr_stub_220
598 .quad isr_stub_221
599 .quad isr_stub_222
600 .quad isr_stub_223
601 .quad isr_stub_224
602 .quad isr_stub_225
603 .quad isr_stub_226
604 .quad isr_stub_227
605 .quad isr_stub_228
606 .quad isr_stub_229
607 .quad isr_stub_230
608 .quad isr_stub_231
609 .quad isr_stub_232
610 .quad isr_stub_233
611 .quad isr_stub_234
612 .quad isr_stub_235
613 .quad isr_stub_236
614 .quad isr_stub_237
615 .quad isr_stub_238
616 .quad isr_stub_239
617 .quad isr_stub_240
618 .quad isr_stub_241
619 .quad isr_stub_242
620 .quad isr_stub_243
621 .quad isr_stub_244
622 .quad isr_stub_245
623 .quad isr_stub_246
624 .quad isr_stub_247
625 .quad isr_stub_248
626 .quad isr_stub_249
627 .quad isr_stub_250
628 .quad isr_stub_251
629 .quad isr_stub_252
630 .quad isr_stub_253
631 .quad isr_stub_254
632 .quad isr_stub_255